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| 001 | 19918506 | ||
| 003 | OSt | ||
| 005 | 20250211144431.0 | ||
| 008 | 170818s2018 flu 001 0 eng | ||
| 010 | _a 2017022734 | ||
| 020 | _a9780367778811 (Pbk : acidfree paper) | ||
| 040 |
_aDLC _beng _erda _cIISERB _dDLC |
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| 042 | _apcc | ||
| 050 | 0 | 0 |
_aTK7868.D5 _bC3948 2018 |
| 082 | 0 | 0 |
_a621.381 C314V _223 |
| 100 | 1 |
_aCavanagh, Joseph. _931394 |
|
| 245 | 1 | 0 |
_aVerilog HDL design examples / _cJoseph Cavanagh. |
| 260 |
_aBoca Raton: _bCRC Press, _c2018. |
||
| 300 |
_axv, 655 pages _c26 cm |
||
| 500 | _aIncludes index. | ||
| 650 | 0 |
_aDigital electronics _xComputer-aided design. _931395 |
|
| 650 | 0 |
_aLogic design. _931396 |
|
| 650 | 0 |
_aVerilog (Computer hardware description language) _931397 |
|
| 906 |
_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg |
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| 942 |
_2ddc _cBK |
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| 999 |
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